Inteview Prep for Serdes Validation Engineer

前職でUSの現地法人に出向していた時に一緒に仕事をしていた友達が、新しい仕事を探しています。Serdes Validation Engineerのpositionに応募する予定だから、Interviewの想定質問と答えを考えて欲しいと頼まれました。自分にとっても、Serdesのテストエンジニアの仕事について、改めて考えてみる良い機会でした。

1. what are the important tests that should be done with serdes PHY beside TX jitters, RX jitter tolerance, jitter transfer, Pll operating range/lock?

1. CDR frequency tracking capability
If Rx has CDR(clock data recovery), Rx clock is allowed to have a slight frequency offset against Tx clock, and CDR absorbs that frequency difference. You want to measure how much frequency difference CDR can absorb.

1.2 CDR lock time
This is very similar to PLL lock time. If there is frequency and phase offset between Tx and Rx, CDR lock time is metric of how long CDR takes to pull-in the frequency offset, and Rx bit-error-ratio becomes zero.

2. Tx/Rx return loss
Return loss is a fancy way of saying 'reflection coefficient' (The difference is reflection coefficients implies DC value and return loss implies frequency dependent value) . Return loss is a metric of how much reflection occurs at Tx or Rx port in condition that transmission line is perfect 50ohm.

3. Power supply noise immunity
Generally Tx jitter is function of power supply noise. Limit of the susceptibility of Tx jitter to supply noise is not clearly defined in the most industry standards. But this metric shows PHY's ultimate competitiveness in realistic environments.

2. What are the other nobs you want to make available to the test chip so that we can tune or debug the serdes performance in the lab. Example for settings Amplitude, pre-amphasis, EQ level settings? internal loop-back...?

1. For PLL measurement, you might want to test different reference frequency and different multiply-ratio. Also you might want to adjust the PLL bandwidth to check how Tx jitter is affected with the bandwidth.

2. For the power supply immunity test, you might want to have noise generation circuit in a test chip. Typical noise generation circuit is bunch of flip-flops.

3. It is very important to make a communication channel in PHY so that these knobs can be controlled from outside even after PHY is integrated into actual ASSP/ASIC products. Typically you want to put Jtag-like interface into PHY for this communication channel.

4. Some high-end PHY have on-die scope capability. Using this capability you can probe eye-diagram at receiver's internal node which shows better indication of receiver voltage and timing margin.

3. Anything else beside the compliance test requirements for standards like PICe or SATA...

Serdes testing is done at mainly three different situation. Each situation has very distinct requirement and restriction.

• Characterization of test chip/product at bench

You will have the biggest control of the PHY. Most thorough tests are done over PVT.

• Manufacturing tests

Moderate controllability but testing time is very limited. Typically only major parameters are tested under min/max voltage condition.

• Debug at customer PCB

Least controllability. It is critical to make communication channel to PHY knobs and PHY's on-die scope.